Western Digital Corp. WDC, announced at the RISC-V Summit three new open-source innovations designed to support Western Digital’s internal RISC-V development efforts and those of the growing RISC-V ecosystem. In his keynote address, Western Digital’s Chief Technology Officer Martin Fink unveiled plans to release a new open source RISC-V core, an open standard initiative for cache coherent memory over a network and an open source RISC-V instruction set simulator. These innovations are expected to accelerate development of new open, purpose-built compute architectures for Big Data and Fast Data environments. Western Digital has taken an active role in helping to advance the RISC-V ecosystem, including multiple related strategic investments and partnerships, and demonstrated progress toward its stated goal of transitioning one billion of the company’s processor cores to the RISC-V architecture.
“As Big Data and Fast Data continues to proliferate, purpose-built technologies are essential for unlocking the true value of data across today’s wide-ranging data-centric applications,” said Fink. “Our SweRV Core and the new cache coherency fabric initiative demonstrate the significant possibilities that can be realized by bringing data closer to processing power. These planned contributions to the open-source community and continued commitment of the RISC-V initiative offer exciting potential to accelerate collaborative innovation and data-driven discoveries.”
RISC-V is an open, scalable instruction set architecture that enables the diversity of Big Data and Fast Data applications and workloads proliferating in core data centers and in remote and mobile systems at the edge.It provides an alternative to current, standard, general purpose compute architectures. With RISC-V, open standard interfaces can be utilized to enable specialty processing, memory centric solutions, unique storage and flexible interconnect applications.
Western Digital is planning to open source its new RISC-V SweRV Core, which has a 2-way superscalar design. Western Digital’s RISC-V SweRV Core is a 32-bit, 9 stage pipeline core that allows several instructions to be loaded at once and execute simultaneously, shortening the time taken to run programs. It is a compact, in-order core and runs at 4.9 CoreMarks/Mhz  . Its power-efficient design offers clock speeds of up to 1.8Ghz  on a 28mm CMOS process technology. The company plans to use the SweRV Core in various internal embedded designs, including flash controllers and SSDs. Open sourcing the core is expected to drive development of new data-centric applications such as Internet of Things (IoT), secure processing, industrial controls and more.
Western Digital’s OmniXtend™ is a new open approach to providing cache coherent memory over an Ethernet fabric. This memory-centric system architecture provides open standard interfaces for access and data sharing across processors, machine learningaccelerators, GPUs, FPGAs and other components. It is an open solution for efficiently attaching persistent memory to processors and offers potential support of future advanced fabrics that connect compute, storage, memory and I/O components.
Western Digital also introduced its open-sourced SweRV Instruction Set Simulator (ISS)™, which offers full test bench support for use with RISC-V cores. An ISS is a computer program that simulates the execution of instructions of a processor. It allows external events to be modeled, such as interrupts and bus errors, and assures the RISC-V core is functioning properly. The company utilized the SweRV ISS to rigorously simulate and validate the SweRV Core, with more than 10 billion instructions executed. Western Digital expects both the SweRV Core and SweRV ISS will help to accelerate the industry’s move to an open source instruction set architecture.
“Speeds, feeds, and brute compute is no longer the winning formula for edge and endpoint computing. As more data moves to the edge for real-time processing and inferencing, configurable architectures will be better suited to meet the needs of heavy and often dynamic application workloads, especially for those driven by artificial intelligence and Internet of Things,” said Mario Morales, program vice president, enabling technologies and semiconductors, IDC. “Power efficiency, configurability, and low power will become the key metrics for edge and endpoint computing architectures.”